1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and particularly to a device and a method of measuring via etch depth and more particularly to a test site and method of monitoring the oxide loss during via etch of overlying metal lines.
2) Description of the Prior Art
Semiconductor technologies have dramatically increased the circuit density upon a chip. The miniaturized devices built in and on a semiconductor substrate are very closely spaced and their packing density has increased significantly. The more recent advances in photolithographic technique, such as phase shifting masks, and self aligning process steps have ever reduced the device size and increased circuit density. This has lead to ultra large scale integration with minimum device dimensions less than a micron and more than a million transistors on a chip. To continue this trend, one challenge facing manufacturers is forming the vias (e.g., holes) through insulating with less etching or damaging the underlying metal lines.
As shown in FIGS. 1 and 2, a conventional semiconductor device is fabricated as follows: semiconductor structures, such as the sources, drains, and gate electrodes, capacitors, insulation layers, etc. are formed in and on a semiconductor substrate 10. Next, a first level metal layer 30 34 is formed over the substrate 10. The first level metal 30 34 often has a top barrier layer 32 36 formed of titanium nitride. The titanium nitrate (TiN) layer 32 36 acts as a barrier to prevent the source gases (e.g., WF.sub.6) form the subsequent tungsten layer from reacting with the first metal layer 30 34 (e.g., aluminum). Without the barrier layer 30 34, an undesired high resistance layer (e.g., AlF.sub.3) could form on the first metal layer and increase the Rc-Via (resistance of the via) and cause Cp yield losses. See FIG. 2.
As shown in FIG. 1, an inter metal dielectric layer 20 is formed over the first metal layer 30 34 and the barrier layer. The inter metal dielectric layer 20 is then planarized to m create a flat level top surface. As shown in FIG. 1, often the underlying topology makes the metal layers 30 34 have different heights and also varies the thickness of the inter metal dielectric layer 20 over the various lines 30 34. As shown for example in FIG. 1, the metal layer 30 is higher than the nearby second metal layer 34.
Next, via's 52 54 are then etched through the inter metal dielectric layer 20 to expose the first level metal 30 32 34 36. The via 52 is shallower than via 54 because the inter metal dielectric layer 20 is thinner over shallow via area 52.
Problems occur where the inter metal dielectric layer has varying thicknesses across the wafer. The metal layers have different underlying structures which cause the inter metal level dielectric layer to be thicker or thinner over a particular metal landing.
This via depth difference or inter metal dielectric thickness difference between product metal lines causes problems. For example, as shown in FIG. 1, in the shallow via 52, the via etch removes a thickness 53 of the TiN layer overlying the first metal 30. If the thickness of TiN barrier layer removed becomes too much, the resistance of the interconnect increases. If the TiN layer is etched through and the metal line is exposed, the interconnect resistance increases significantly. The increased interconnect resistance causes circuit performance problems and Cp yield losses.
Referring to FIG. 2, an interconnect 60 is formed in the via 52 54 and then a second metal layer 62 is formed over the interconnect 60. If the via etch breaks through the titanium nitride layers 32 36, the resistance of the interconnect increases abruptly. Increasing the thickness of the titanium nitride layer could reduce the via overetch problem but this lowers process throughput and creates step coverage problems.
Other practitioners in the art have work on other semiconductor problems. U.S. Pat. No. 5,494,697 (Blayo) shows a thickness monitoring with an ellipsometer. U.S. Pat. No. 5,229,309 (Cheng) and U.S. Pat. No. 5,451,529 (Hsu) show other monitoring methods. However, these patents do not adequately solve the problem of preventing via over etch. Therefore there is a need to develop a method and a device to easily measure the via etch so that the via etch process can be more easily controlled.